The present invention relates generally to analog to digital converters, and more specifically to an improvement in charge redistribution analog to digital converters.
Analog to digital converters include three distinctive phases of a cycled operation, namely an adjustment phase for offset or gain, an input acquisition phase, and a conversion phase. These phases are described specifically in Raymond B. Patterson, III U.S. Pat. No. 4,282,515. Analog to digital converters using charge redistribution techniques provide an inherent sample-and-hold function for acquisition as well as offset adjustment or cancellation. Such a system is described in an article "All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques--Part 1", J. McCreary and P. Gray, IEEE, J. Solid State Circuits, vol. Sc-10, pp. 371-379, December 1975. A block diagram of an analog-to-digital converter is illustrated in FIG. 1 as including, for example, an eight-bit successive approximation register, a current controlled oscillator and timing generator, an eight-bit weighted capacitor array constituting a digital-to-analog converter, high speed analog comparator, and a latch. Input and output buffers are included to provide digital inputs and outputs. A controller is provided which receives the input analog signal V.sub.IN, a reference signal V.sub.REF, an analog ground and a start conversion command signal SC, which may be a digital-or-analog input signal. The controller controls the circuity of FIG. 1 to produce the sequence illustrated in the graphs of FIG. 2.
As illustrated in FIG. 2, upon receipt of the start command signal SC the capacitors of the array are discharged by connecting both terminals to ground in response to a discharge signal DC. Upon completion of the discharging of the capacitive array, which takes approximately 100 nanoseconds, after which acquisition cycle begins. After a settling time of approximately 100-200 nanoseconds, allowing for the transient loading effects, the offset cancellation of the comparator begins and is illustrated by the pulse SO. This is the first phase of the circuits adjustment and compensation as described above.
The acquisition cycle, illustrated by the signal ACQ, lasts approximately 700 nanoseconds and begins with the sampling of the comparator offset. Only after acquisition of an analog input signal, provided as an input to the capacitor array, has been completed, can the successive approximation portion of the cycle or conversion begin. The successive approximation cycle is represented by the eight cycles of SAR for the eight-bit successive approximation register and takes approximately 1 microsecond. Upon termination of the successive approximation routine, the digital value is fixed by latching, illustrated by the LATCH signal in the graphs of FIG. 2.
The elapsed time between the start conversion command SC and the beginning of the successive approximation routine SAR, is approximately 1.1 microseconds. This is an aperture delay defined as the time lag between the start conversion command and the instant when the input is actually held on the capacitor array. With internal timing generation, it is not apparent to the user when the sampling of the input signal is completed and the exact instance when the conversion starts. This sequence makes the converter unsuitable for digital signal processing applications, where the instance at which the input is sampled is very important.
Also aperture jitter, defined as the uncertainty in time between the hold or termination of acquisition command and the instant the analog input is actually disconnected from the capacitor array, is important. In prior art methods, this signal is internally generated by a ramp and a comparator and the aperature jitter is in the range of 10 to 100 nanoseconds.
Thus, it is an object of the present invention to provide an analog-to-digital converter using charge redistribution which is suitable for digital signal processing applications.
Another object of the present invention is to provide a analog-to-digital converter using charge redistribution with reduced aperture delay and aperture jitter.
These and other objects of the invention are achieved by terminating the acquisition phase of the analog input signal and immediately starting the successive approximation conversion phase upon receipt of a start conversion command signal. Upon the completion of the successive approximation conversion phase, the result is fixed by latching. This is followed by the discharge of the capacitor array and initiation of the acquisition phase and of sample-and-holding or cancelling for the comparator offset. The acquisition phase begins at the termination of the discharge of the capacitor array, and continues until the receipt or occurrence of the next start conversion command. Thus, the present invention reduces the aperture jitter and aperture delay to substantially zero and performs the discharge, offset correction and acquisition phase after the termination of the conversion phase and will be referred to as the "back-sampling" technique. Initiating the successive approximation conversion phase using the start conversion command signal reduces aperture jitter.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.